Python Embedding in SystemVerilog

Goal: Initialize and finalize the Python interpreter from SystemVerilog.

This SystemVerilog code snippet showcases Python Embedding in SystemVerilog through the use of PyStim. This integration is particularly valuable when you want to leverage Python’s extensive libraries or scripting power to enhance your hardware design and verification workflows.

import pystim_pkg::*;

module hello_world();
    typedef pystim py;

    initial begin
        py::initialize_interpreter();
        begin
            automatic py_dict globals = py::globals();
            automatic py_dict locals = py_dict::create_empty();

            locals.set(py::str_("name"),py::str_("Python"));
            py::exec("print('Hello from {}!'.format(name))", globals, locals);
        end
        py::finalize_interpreter();
    end
    
endmodule

The py::exec function is then used to execute a Python code. The script, "print('Hello from {}!'.format(name))", prints a formatted string that includes the value of the name variable. The globals and locals dictionaries are passed as arguments to py::exec, ensuring that the script has access to the defined variables and namespaces.

The exec method returns the execution status. If a Python code execution error occurs, it will return an instance of the py_error class, which contains details of the Python exception. Otherwise, it will return an object of type py_none.

It’s a good idea to check the execution status before proceeding. You can also enable Python exception printing and halt the SystemVerilog simulation if a Python exception occurs.